1. Field of the Invention
The present invention relates to a semiconductor tester for testing a device under test (DUT) with a plurality of ports whose periods (frequencies) are different. More particularly, the present invention relates to a semiconductor tester capable of generating a test pattern by which a DUT with a plurality of ports whose periods are different can be tested without a plurality of timing memories for storing finite timing sets. In addition, the present application claims the benefit of, and priority to, Japanese patent application No. 2001-354220 filed on Nov. 20, 2001, the entire contents of which are incorporated herein by reference for all purposes.
2. Related Art
FIG. 1 shows the schematic configuration of a semiconductor tester. The main configuration elements include a timing generator TG, a pattern generator PG, a waveform formatter FC, a pin electronics PE, and a logic comparator DC. The pin electronics PE includes a driver DR, a comparator CP, etc. Here, since the semiconductor tester is publicly known and it is technically well known, the signals or configuration elements except the main elements related to this invention will not be described in detail.
FIG. 2 shows an example of a DUT which includes two ports required to have different periods (two kinds of periods). The DUT includes a FIFO memory and a built-in PLL oscillator therein. The built-in PLL oscillator generates a clock frequency, which results from receiving an input clock CLKIN and converting it at the rate of N/M, and supplies it to a retrieving clock input terminal RCLK of the FIFO.
FIG. 3 shows a timing chart where the DUT in FIG. 2 is tested with a test period (test rate) being set as a period N in accordance with a conventional semiconductor tester.
As shown in FIG. 3, since DATAIN and CLKIN operate with the period M if the test rate is cut out by the unit of the period N, it is inevitable to divide and attach different timing set signals (TS signals) TS1 to TS8 for each cycle. However, because of a simple period (least common multiple period P) in this case where the period M times 7 and the period N times 8 make one round, a circulation is completed with 8 of the TS signals TS1 to TS8. In a practical DUT test, however, various period conditions are required. The number of the timing sets to be used (number of TS) is required to be (the least common multiple period of the periods M and N)/the period N.
Meanwhile, the number of TS provided to the semiconductor tester is finite as many as 1024. In case of the condition which exceeds that number, there is a problem that the device test is difficult. Otherwise, it is necessary to increase the number of TS. The timing sets are provided in an LSI for each test channel. Besides, it is required to be changeable with the on-the-fly, and it is required to be capable of operating at a maximum test rate, e.g. 500 MHz. Accordingly, increasing the memory capacity of the timing sets up to two or four times the capacity causes a problem that the number of the test channels which can be mounted in an LSI decreases. Further, the increase of the memory capacity leads to a problem of high cost.
FIG. 4 shows a timing chart where a test pattern in response to the periods M and N is generated with timing sets provided in a practical semiconductor tester being applied. The test rate of the semiconductor tester fits into the period N of the DATAOUT side, so CLKIN and DATAIN of the period M is required to supply a pattern to be applied which has been delayed by a predetermined amount in order that timing edges should exist at predetermined positions respectively by sequentially changing the TS signals for each cycle using 8 TSs, i.e. TS1 to TS8.
FIG. 5 shows an example of the test pattern in response to the timing chart in FIG. 4. This is a test pattern cut out with the test rate being taken as the period N. Herein, “NOP” is a sequence instruction indicating to proceed to the next address in case of performing the pattern of that address, and “STOP” is an instruction to complete the generation of the pattern in case of performing the pattern of that address. TS1 to TS8 are the delay data to designate the delay amount from each start point of the period N for each cycle edge. Pluses are generated at the timing which has been delayed by a predetermined amount for each cycle on the basis of the TSs. Furthers All of them are stored in a pattern memory (not shown) inside the pattern generator PG.
FIG. 6 shows a block diagram of a timing generator TG, a waveform formatter FC, and a logic comparator DC in the conventional art, depicting one of tester channels. Further, the tester channels depend upon the system configuration, and hundreds or thousands of channels are provided.
TG related to this invention accesses a timing set memory TSM for storing delay information and supplies a plurality of edge pluses TDT which are the result of delaying timing pulses with variable delay means d22 by a predetermined amount in the corresponding cycle based on a timing set signal TTS which is the result of receiving a timing set signal PGTS that designates the timing set from PG shown in FIG. 1 via a test period generating unit 10. And it outputs a test rate clock TRATE indicating the test rate.
FC related to this invention includes a FIFO 42 and a formatting unit 44. The FIFO 42 receives a test pattern PAT1 from PG, stores it in a buffer with a rate clock RATECLK, and supplies FIFO output data 42s which is the result of retrieving the content stored in the FIFO at the timing of the test rate clock TRATE to the formatting unit 44.
The formatting unit 44 receives the output data 42s of the FIFO, and outputs a drive pulse DRP, which is the result of receiving a predetermined number of edge pulses TDT and formatting them into a predetermined waveform to be applied, to the DUT via the pin electronics.
DC related to this invention includes a FIFO 52 and a comparator 54. The FIFO 52 receives an expected value pattern PAT2 from PG, stores it in a buffer with the rate clock RATECLK, and supplies FIFO output data 52s which is the result of retrieving the content stored in the FIFO at the timing of the test rate clock TRATE to the comparator 54.
The comparator 54 receives the FIFO output data 52s, receives a plurality of edge pulses TDT as a strobe signal, and outputs a fail signal FL which is the result of judging the quality of a comparator signal CPD that is a response signal from the DUT under a predetermined comparison condition.
According to the conventional configuration in FIG. 6 as described above, it is necessary to apply a test pattern in FIG. 5 to the waveform of the timing chart shown in FIG. 4. Consequently, even in case of two kinds of periods and in a simple case that the least common multiple period P is 8, 8 numbers of TSs, i.e. TS1 to TS8 are consumed. In case of 3 kinds of periods, the least common multiple period P for the 3 kinds of periods becomes a larger value. If the least common multiple period P exceeds 1024, the test becomes impossible, and it is necessary to considerably increase the timing memory as much as two or four times. In this regard, the semiconductor tester of the conventional configuration has a practical problem which is not preferable.